View DM9008AEP_4395959.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DM9008AEP ethernet controller with general processor interface preliminary 1 version: dm9008a-ds-p02 apr. 11, 2006 davicom semiconductor, inc. DM9008AEP ethernet controller with general processor interface data sheet preliminary version: DM9008AEP-ds-p03 dec. 14, 2006
DM9008AEP ethernet controller with general processor interface preliminary 2 version: dm9008a-ds-p02 apr. 11, 2006 content 1. general description......................................................................................................... .. 6 2. block diagram............................................................................................................... ..... 6 3. features.................................................................................................................... .......... 7 4. pin configuration........................................................................................................... .... 8 5. pin description ............................................................................................................. ..... 9 5.1 processor interface........................................................................................................ ........................... 9 5.2 eeprom interface ........................................................................................................... ........................ 9 5.3 clock interface ............................................................................................................ ............................ 10 5.4 led interface .............................................................................................................. ............................ 10 5.5 10/100 phy/fiber ........................................................................................................... ........................ 10 5.6 miscellaneous .............................................................................................................. ........................... 10 5.7 power pins................................................................................................................. ............................. 11 5.8 strap pins table........................................................................................................... ............................. 11 6. vendor control and status register set ....................................................................... 12 6.1 network control register (00h)............................................................................................. ................. 13 6.2 network status register (01h) .............................................................................................. ................. 14 6.3 tx control register (02h) .................................................................................................. .................... 14 6.4 tx status register i ( 03h ) for packet index i ............................................................................ ........... 14 6.5 tx status register ii ( 04h ) for packet index i i ......................................................................... ........... 15 6.6 rx control register ( 05h )................................................................................................ .................... 15 6.7 rx status register ( 06h ) ................................................................................................. .................... 15 6.8 receive overflow counter register ( 07h ) .................................................................................. ......... 16 6.9 back pressure threshold register (08h) ..................................................................................... .......... 16 6.10 flow control threshold register ( 09h ) ................................................................................... ........... 16 6.11 rx/tx flow control register ( 0ah ) ....................................................................................... ............ 17 6.12 eeprom & phy control register ( 0bh )..................................................................................... ...... 17 6.13 eeprom & phy address register ( 0ch ) ..................................................................................... .... 17 6.14 eeprom & phy data register (ee_phy_l j 0dh ee_phy_h j 0eh)........................................ 17 6.15 wake up control register ( 0fh ) (in 8-bit mode) .......................................................................... ..... 18 6.16 physical address register ( 10h~15h ) ..................................................................................... .......... 18 6.17 multicast address register ( 16h~1dh ).................................................................................... .......... 18
DM9008AEP ethernet controller with general processor interface preliminary 3 version: dm9008a-ds-p02 apr. 11, 2006 6.18 general purpose control register ( 1eh ) (in 8-bit mode) ................................................................. 18 6.19 general purpose register ( 1fh ) .......................................................................................... .............. 19 6.20 tx sram read pointer address register (22h~23h) ........................................................................ 19 6.21 rx sram write pointer address register (24h~25h) ........................................................................ 19 6.22 vendor id register (28h~29h) .............................................................................................. .............. 19 6.23 product id register (2ah~2bh)............................................................................................. .............. 19 6.24 chip revision register (2ch).............................................................................................. ................. 19 6.25 transmit control register 2 ( 2dh ) ....................................................................................... .............. 19 6.26 operation test control register ( 2eh ) ................................................................................... ........... 20 6.27 special mode control register ( 2fh )..................................................................................... ............ 20 6.28 early transmit control/status register ( 30h ) ............................................................................ ........ 21 6.29 check sum control register ( 31h ) ........................................................................................ ............ 21 6.30 receive check sum status register ( 32h ) ................................................................................. ...... 21 6.31 led pin control register ( 34h ).......................................................................................... ................ 21 6.32 processor bus control register ( 38h ) .................................................................................... ........... 22 6.33 int pin control register ( 39h ).......................................................................................... ................. 23 6.34 system clock turn on control register ( 50h )............................................................................. ..... 23 6.35 resume system clock control register ( 51h ) .............................................................................. .... 23 6.36 memory data pre-fetch read command without add ress increment register (f0h) ....................... 24 6.37 memory data read command without address increment register (f1h) ........................................ 24 6.38 memory data read command with address increment register (f2h) ............................................. 24 6.39 memory data read_address register (f4h~f5h) .............................................................................. 2 4 6.40 memory data write command without address increment register (f6h)......................................... 24 6.41 memory data write command with address increment register (f8h) ................................................ 24 6.42 memory data write_address register (fah~fbh).............................................................................. .24 6.43 tx packet length register (fch~fdh) ....................................................................................... ....... 24 6.44 interrupt status register (feh) ........................................................................................... ................. 25 6.45 interrupt mask register (ffh) ............................................................................................. ................. 25 7. eeprom format .............................................................................................................. 2 6 8. mii register description.................................................................................................. 27 8.1 basic mode control register (bmcr) - 00.................................................................................... ......... 27 8.2 basic mode status register (bmsr) - 01 ..................................................................................... ......... 29 8.3 phy id identifier register #1 (phyid1) - 02................................................................................ .......... 30 8.4 phy id identifier register #2 (phyid2) - 03................................................................................ .......... 30
DM9008AEP ethernet controller with general processor interface preliminary 4 version: dm9008a-ds-p02 apr. 11, 2006 8.5 auto-negotiation advertisement register (anar) - 04 ........................................................................ .. 31 8.6 auto-negotiation link partner ability register (anlpar) ? 05 .............................................................. 3 2 8.7 auto-negotiation expansion register (aner)- 06............................................................................. ..... 33 8.8 davicom specified configuration register (dscr) ? 16..................................................................... 33 reserved ....................................................................................................................... ....... 34 force to 0 in application. .................................................................................................... 3 4 8.9 davicom specified configuration and status register (dscsr) - 17................................................. 35 8.10 10base-t configuration/status (10btcsr) - 18 .............................................................................. .. 36 8.11 (specified config) register ? 20.......................................................................................... .................. 36 9. functional description.................................................................................................... 38 9.1 host interface............................................................................................................. ............................. 38 9.2 direct memory access control ............................................................................................... ................ 38 9.3 packet transmission........................................................................................................ ....................... 38 9.4 packet reception........................................................................................................... ......................... 38 9.5 10base-t operation......................................................................................................... ....................... 39 9.6 collision detection ........................................................................................................ .......................... 39 9.7 carrier sense.............................................................................................................. ............................ 39 9.8 auto-negotiation ........................................................................................................... .......................... 39 9.9 power reduced mode ......................................................................................................... ................... 40 9.9.1 power down mode .......................................................................................................... .................... 40 9.9.2 reduced transmit power mode .............................................................................................. ............ 40 10. dc and ac electrical characteristics .......................................................................... 41 10.1 absolute maximum ratings ( 25 c )..................................................................................................... 41 10.1.1 operating conditions .................................................................................................... ..................... 41 10.2 dc electrical characteristics (vdd = 3.3v)................................................................................ .......... 41 10.3 ac electrical characteristics & timing waveforms.......................................................................... .... 42 10.3.1 oscillator/crystal timing............................................................................................... ..................... 42 10.3.2 processor i/o read timing ............................................................................................... ................ 42 10.4.3 processor i/o write timing.............................................................................................. .................. 43 10.4.4 eeprom interface timing ................................................................................................. ............... 44 11. application notes .......................................................................................................... 45 11.1 network interface signal routing .......................................................................................... ............... 45 hp auto-mdix application....................................................................................................... ..................... 45 11.3 non hp auto-mdix transformer application .................................................................................. ..... 46
DM9008AEP ethernet controller with general processor interface preliminary 5 version: dm9008a-ds-p02 apr. 11, 2006 11.4 power decoupling capacitors ............................................................................................... ............... 46 11.41 dm9008a + dm8606a circuit ................................................................................................ ............ 47 11.5 magnetics selection guide ................................................................................................. .................. 48 11.6 crystal selection guide ................................................................................................... ..................... 48 12. package information ..................................................................................................... 49 13. ordering information..................................................................................................... 50
DM9008AEP ethernet controller with general processor interface preliminary 6 version: dm9008a-ds-p02 apr. 11, 2006 1. general description the dm9008a is a fully integrated and cost-effective low pin count ethernet controller with a general processor interface, a medial access control (mac), a 10base-t phy and 16k byte sram. it is designed with low power and high performance process that support 3.3v with 5v io tolerance. the dm9008a supports 8-bit and 16-bit data interfaces to internal memory accesses for various processors. the dm9008a also supports full duplex mode the phy of the dm9008a can interface to the utp3, 4, 5 in 10base-t that is fully compliant with the ieee 802.3 spec.. the hp auto-mdix function of phy is also supported to improve the media connection in convenience. 2. block diagram
DM9008AEP ethernet controller with general processor interface preliminary 7 version: DM9008AEP-ds-p03 dec. 14, 2006 3. features ? 48-pin lqfp ? supports processor interface: byte/word of i/o command to internal memory data operation ? comply to 10base-t of ieee 802.3 with hp auto-mdix ? supports back pressure mode for half-duplex mode flow control ? support 100m fiber interface. ? ieee802.3x flow control for full-duplex mode ? supports wakeup frame, link status change and magic packet events for remote wake up ? integrated 16k byte sram ? build in 3.3v to 2.5v regulator ? supports early transmit ? supports automatically load vendor id and product id from eeprom ? optional eeprom configuration ? very low power consumption mode: y power reduced mode (cable detection) y power down mode y selectable tx drivers for 1:1 or 1.25:1 transformers for additional power reduction. ? compatible with 3.3v and 5.0v tolerant i/o
DM9008AEP ethernet controller with general processor interface preliminary 8 version: DM9008AEP-ds-p03 dec. 14, 2006 4. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 37 38 39 40 41 42 43 44 45 46 47 48 bgres txvdd25 rx+ tx- rx- rxgnd txgnd tx+ rxvdd25 sd7 sd6 sd5 cs# led2 led1 test pwrst# vdd x2 x1 gnd sd rxgnd bggnd 13 14 15 16 17 18 19 20 21 22 23 24 eedio sd4 sd3 gnd sd2 sd1 sd0 eecs sd15_wake vdd eeck sd14_led3 35 36 34 33 32 31 30 29 28 27 26 25 sd13_gp6 sd9_gp2 sd11_gp4 sd12_gp5 sd10_gp3 vdd sd8_gp1 cmd int gnd ior# iow# dm9008a
DM9008AEP ethernet controller with general processor interface preliminary 9 version: DM9008AEP-ds-p03 dec. 14, 2006 5. pin description i = input o = output i/o = input/output o/d = open drain p = power # = asserted low pd = internal pull-low about 60k 5.1 processor interface pin no. pin name type description 35 ior# i,pd processor read command this pin is low active at default, its polarity can be modified by eeprom setting. see the eeprom content description for detail 36 iow# i,pd processor write command this pin is low active at default, its polarity can be modified by eeprom setting. see the eeprom content description for detail 37 cs# i,pd chip select a default low active signal used to select the dm9008a. its polarity can be modified by eeprom setting. see the eeprom content description for detail. 32 cmd i,pd command type when high, the access of this command cycle is data port when low, the access of this command cycle is index port 34 int o,pd interrupt request this pin is high active at default, its polarity can be modified by eeprom setting or by strap pin eeck. see the eeprom content description for detail 18,17,16,1 4,13,12,11 ,10 sd0~7 i/o,pd processor data bus bit 0~7 31, 29, 28, 27, 26, 25, 24, 22 sd8_gp1, sd9_gp2, sd10_gp3, sd11_gp4, sd12_gp5, sd13_gp6, sd14_led3, sd15_wake i/o,pd processor data bus bit 8~15 in 16-bit mode (see eecs pin description), these pins act as the processor data bus bit 8~15; in 8-bit mode, these pins have other definitions in the followings: pin 31,29,28,27,26,25 act as the general purpose pins that defined in reg.1eh and 1fh. the sd13_ gp6 pin also act as trap pin for the int output type. when sd13_gp6 is pulled high, the int is open-drain output type; otherwise it is force output type. pin 24 is act as full-duplex led in led mode 1; otherwise it act as 10base-t link led in led mode 0. (note: led mode is defined in eeprom setting.) pin 22 is act as a wake up signal. 5.2 eeprom interface pin no. pin name type description 19 eedio i/o,pd io data to eeprom 20 eeck o,pd clock to eeprom this pin is also used as the strap pin of the polarity of the int pin when this pin is pulled high, the int pin is low active; otherwise the int pin is high active 21 eecs o,pd chip select to eeprom this pin is also used as a strap pin to define the internal memory data bus width. when it is pulled high, the memory access bus is 8-bit; otherwise it is 16-bit.
DM9008AEP ethernet controller with general processor interface preliminary 10 version: DM9008AEP-ds-p03 dec. 14, 2006 5.3 clock interface pin no. pin name type description 43 x2 o crystal 25mhz out 44 x1 i crystal 25mhz in 5.4 led interface pin no. pin name type description 39 led1 o speed led its low output indicates that the internal phy is operated in 100m/s, or it is floating for the 10m mode of the internal phy. this pin also acts as isa bus io16 function defined in eeprom setting. 38 led2 o link / active led in led mode 1, it is the combined led of link and carrier sense signal of the internal phy in led mode 0, it is the led of the carrier sense signal of the internal phy only 5.5 10/100 phy/fiber pin no. pin name type description 46 sd i fiber-optic signal detect pecl signal, which indicates whether or not the fiber-optic receive pair is receiving valid levels 48 bggnd p bandgap ground 1 bgres i/o bandgap pin 2 rxvdd25 p 2.5v power output for tp rx 9 txvdd25 p 2.5v power output for tp tx 3 rx+ i/o tp rx input 4 rx- i/o tp rx input 5,47 rxgnd p rx ground 6 txgnd p tx ground 7 tx+ i/o tp tx output 8 tx- i/o tp tx output 5.6 miscellaneous pin no. pin name type description 41 test i operation mode force to ground in normal application 40 pwrst# i power on reset active low signal to initiate the dm9008a the dm9008a is ready after 5us when this pin deasserted
DM9008AEP ethernet controller with general processor interface preliminary 11 version: DM9008AEP-ds-p03 dec. 14, 2006 5.7 power pins pin no. pin name type description 23,30,42 vdd p digital vdd 3.3v power input 15,33,45 gnd p digital gnd 5.8 strap pins table 1: pull-high 1k~10k, 0: floating (default) pin no. pin name description 20 eeck polarity of int 1: int pin low active; 0: int pin high active 21 eecs data bus width 1: 8-bit 0: 16-bit 22 wake polarity of cs# in 8-bit mode 1: cs# pin active high 0: cs# pin active low 25 sd13_gp6 int output type in 8-bit mode 1: open-drain 0: force mode
DM9008AEP ethernet controller with general processor interface preliminary 12 version: DM9008AEP-ds-p03 dec. 14, 2006 6. vendor control and status register set the dm9008a implements several control and status registers, which can be accessed by the host. these csrs are byte aligned. all csrs are set to their default values by hardware or software reset unless they are specified register description offset default value after reset ncr network control register 00h 00h nsr network status register 01h 00h tcr tx control register 02h 00h tsr i tx status register i 03h 00h tsr ii tx status register ii 04h 00h rcr rx control register 05h 00h rsr rx status register 06h 00h rocr receive overflow counter register 07h 00h bptr back pressure threshold register 08h 37h fctr flow control threshold register 09h 38h fcr rx flow control register 0ah 00h epcr eeprom & phy control register 0bh 00h epar eeprom & phy address register 0ch 40h epdrl eeprom & phy low byte data register 0dh xxh epdrh eeprom & phy high byte data register 0eh xxh wcr wake up control register (in 8-bit mode) 0fh 00h par physical address register 10h-15h determined by eeprom mar multicast address register 16h-1dh xxh gpcr general purpose control register (in 8-bit mode) 1eh 01h gpr general purpose register 1fh xxh trpal tx sram read pointer address low byte 22h 00h trpah tx sram read pointer address high byte 23h 00h rwpal rx sram write pointer address low byte 24h 00h rwpah rx sram write pointer address high byte 25h 0ch vid vendor id 28h-29h 0a46h pid product id 2ah-2bh 9000h chipr chip revision 2ch 19h tcr2 tx control register 2 2dh 00h ocr operation control register 2eh 00h smcr special mode control register 2fh 00h etxcsr early transmit control/status register 30h 00h tcscr transmit check sum control register 31h 00h rcscsr receive check sum control status register 32h 00h ledcr led pin control register 34h 00h buscr processor bus control register 38h 61h intcr int pin control register 39h 00h sccr system clock turn on control register 50h 00h rsccr resume system clock control register 51h xxh
DM9008AEP ethernet controller with general processor interface preliminary 13 version: DM9008AEP-ds-p03 dec. 14, 2006 mrcmdx memory data pre-fetch read command without address increment register f0h xxh mrcmdx1 memory data read command with address increment register f1h xxh mrcmd memory data read command with address increment register f2h xxh mrrl memory data read_ address register low byte f4h 00h mrrh memory data read_ address register high byte f5h 00h mwcmdx memory data write command without address increment register f6h xxh mwcmd memory data write command with address increment register f8h xxh mwrl memory data write_ address register low byte fah 00h mwrh memory data write _ address register high byte fbh 00h txpll tx packet length low byte register fch xxh txplh tx packet length high byte register fdh xxh isr interrupt status register feh 00h imr interrupt mask register ffh 00h key to default in the register description that follows, the default column takes the form: , where j : 1 bit set to logic one 0 bit set to logic zero x no default value p = power on reset default value h = hardware reset default value s = software reset default value e = default value from eeprom t = default value from strap pin : ro = read only rw = read/write r/c = read and clear rw/c1=read/write and cleared by write 1 wo = write only reserved bits are shaded and should be written with 0. reserved bits are undefined on read access. 6.1 network control register (00h) bit name default description 7 reserved ph0,rw reserved 6 wakeen p0,rw wakeup event enable work in 8-bit mode when set, it enables the wakeup function. clearing this bit will also clears all wakeup event status this bit will not be affected after a software reset 5 reserved 0,ro reserved 4 fcol phs0,rw force collision mode, used for testing 3 fdx phs0,ro full-duplex mode of the internal phy. 2:1 lbk phs00, rw loopback mode bit 2 1 0 0 normal 0 1 mac internal loopback 1 x (reserved) 0 rst ph0,rw software reset and auto clear after 10us
DM9008AEP ethernet controller with general processor interface preliminary 14 version: DM9008AEP-ds-p03 dec. 14, 2006 6.2 network status register (01h) bit name default description 7 reserved x,ro reserved 6 linkst x,ro link status 0:link failed 1:link ok, 5 wakest p0, rw/c1 wakeup event status. clears by read or write 1 (work in 8-bit mode) this bit will not be affected after software reset 4 reserved 0,ro reserved 3 tx2end phs0, rw/c1 tx packet 2 complete status. clears by read or write 1 transmit completion of packet index 2 2 tx1end phs0, rw/c1 tx packet 1 complete status. clears by read or write 1 transmit completion of packet index 1 1 rxov phs0,ro rx fifo overflow 0 reserved 0,ro reserved 6.3 tx control register (02h) bit name default description 7 reserved 0,ro reserved 6 tjdis phs0,rw transmit jabber disable when set, the transmit jabber timer (2048 bytes) is disabled. otherwise it is enable 5 excecm phs0,rw excessive collision mode control : 0:aborts this packet when excessive collision counts more than 15, 1: still tries to transmit this packet 4 pad_dis2 phs0,rw pad appends disable for packet index 2 3 crc_dis2 phs0,rw crc appends disable for packet index 2 2 pad_dis1 phs0,rw pad appends disable for packet index 1 1 crc_dis1 phs0,rw crc appends disable for packet index 1 0 txreq phs0,rw tx request. auto clears after sending completely 6.4 tx status register i ( 03h ) for packet index i bit name default description 7 tjto phs0,ro transmit jabber time out it is set to indicate that the transmitted frame is truncated due to more than 2048 bytes are transmitted 6 lc phs0,ro loss of carrier it is set to indicate the loss of carrier during the frame transmission. it is not valid in internal loopback mode 5 nc phs0,ro no carrier it is set to indicate that there is no carrier signal during the frame transmission. it is not valid in internal loopback mode 4 lc phs0,ro late collision it is set when a collision occurs after the collision window of 64 bytes 3 col phs0,ro collision packet it is set to indicate that the collision occurs during transmission 2 ec phs0,ro excessive collision it is set to indicate that the transmission is aborted due to 16 excessive collisions 1:0 reserved 0,ro reserved
DM9008AEP ethernet controller with general processor interface preliminary 15 version: DM9008AEP-ds-p03 dec. 14, 2006 6.5 tx status register ii ( 04h ) for packet index i i bit name default description 7 tjto phs0,ro transmit jabber time out it is set to indicate that the transmitted frame is truncated due to more than 2048 bytes are transmitted 6 lc phs0,ro loss of carrier it is set to indicate the loss of carrier during the frame transmission. it is not valid in internal loopback mode 5 nc phs0,ro no carrier it is set to indicate that there is no carrier signal during the frame transmission. it is not valid in internal loopback mode 4 lc phs0,ro late collision it is set when a collision occurs after the collision window of 64 bytes 3 col phs0,ro collision packet, collision occurs during transmission 2 ec phs0,ro excessive collision it is set to indicate that the transmission is aborted due to 16 excessive collisions 1:0 reserved 0,ro reserved 6.6 rx control register ( 05h ) bit name default description 7 reserved phs0,rw reserved 6 wtdis phs0,rw watchdog timer disable when set, the watchdog timer (2048 bytes) is disabled. otherwise it is enabled 5 dis_long phs0,rw discard long packet packet length is over 1522byte 4 dis_crc phs0,rw discard crc error packet 3 all phs0,rw pass all multicast 2 runt phs0,rw pass runt packet 1 prmsc phs0,rw promiscuous mode 0 rxen phs0,rw rx enable 6.7 rx status register ( 06h ) bit name default description 7 rf phs0,ro runt frame it is set to indicate that the size of the received frame is smaller than 64 bytes 6 mf phs0,ro multicast frame it is set to indicate that the received frame has a multicast address 5 lcs phs0,ro late collision seen it is set to indicate that a late collision is found during the frame reception 4 rwto phs0,ro receive watchdog time-out it is set to indicate that it receives more than 2048 bytes 3 ple phs0,ro physical layer error it is set to indicate that a physical layer error is found during the frame reception 2 ae phs0,ro alignment error it is set to indicate that the received frame ends with a non-byte boundary 1 ce phs0,ro crc error it is set to indicate that the received frame ends with a crc error 0 foe phs0,ro fifo overflow error it is set to indicate that a fifo overflow error happens during the frame reception
DM9008AEP ethernet controller with general processor interface preliminary 16 version: DM9008AEP-ds-p03 dec. 14, 2006 6.8 receive overflow counter register ( 07h ) bit name default description 7 rxfu phs0,r/c receive overflow counter overflow this bit is set when the roc has an overflow condition 6:0 roc phs0,r/c receive overflow counter this is a statistic counter to indicate the received packet count upon fifo overflow 6.9 back pressure threshold register (08h) bit name default description 7:4 bphw phs3, rw back pressure high water overflow threshold. mac will generate the jam pattern when rx sram free space is lower than this threshold value the default is 3k-byte free space. please do not exceed sram size (1 unit=1k bytes) 3:0 jpt phs7, rw jam pattern time. default is 200us bit3 bit2 bit1 bit0 time 0 0 0 0 5us 0 0 0 1 10us 0 0 1 0 15us 0 0 1 1 25us 0 1 0 0 50us 0 1 0 1 100us 0 1 1 0 150us 0 1 1 1 200us 1 0 0 0 250us 1 0 0 1 300us 1 0 1 0 350us 1 0 1 1 400us 1 1 0 0 450us 1 1 0 1 500us 1 1 1 0 550us 1 1 1 1 600us 6.10 flow control threshold register ( 09h ) bit name default description 7:4 hwot phs3, rw rx fifo high water overflow threshold send a pause packet with pause_ time=ffffh when the rx ram free space is less than this value., if this value is zero, its means no free rx sram space. the default value is 3k-byte free space. please do not exceed sram size (1 unit=1k bytes) 3:0 lwot phs8, rw rx fifo low water overflow threshold send a pause packet with pause_time=0000 when rx sram free space is larger than this value. this pause packet is enabled after the high water pause packet is transmitted. the default sram free space is 8k-byte. please do not exceed sram size (1 unit=1k bytes)
DM9008AEP ethernet controller with general processor interface preliminary 17 version: DM9008AEP-ds-p03 dec. 14, 2006 6.11 rx/tx flow control register ( 0ah ) bit name default description 7 txp0 hps0,rw tx pause packet auto clears after pause packet transmission completion. set to tx pause packet with time = 0000h 6 txpf hps0,rw tx pause packet auto clears after pause packet transmission completion. set to tx pause packet with time = ffffh 5 txpen hps0,rw force tx pause packet enable enables the pause packet for high/low water threshold control 4 bkpa hps0,rw back pressure mode this mode is for half duplex mode only. it generates a jam pattern when any packet comes and rx sram is over bphw of register 8. 3 bkpm hps0,rw back pressure mode this mode is for half duplex mode only. it generates a jam pattern when a packet?s da matches and rx sram is over bphw of register 8. 2 rxps hps0,r/c rx pause packet status, latch and read clearly 1 rxpcs hps0,ro rx pause packet current status 0 flce hps0,rw flow control enable set to enable the flow control mode (i.e. can disable dm9008a tx function) 6.12 eeprom & phy control register ( 0bh ) bit name default description 7:6 reserved 0,ro reserved 5 reep ph0,rw reload eeprom. driver needs to clear it up after the operation completes 4 wep ph0,rw write eeprom enable 3 epos ph0,rw eeprom or phy operation select when reset, select eeprom; when set, select phy 2 erprr ph0,rw eeprom read or phy register read command. driver needs to clear it up after the operation completes. 1 erprw ph0,rw eeprom write or phy register write command. driver needs to clear it up after the operation completes. 0 erre ph0,ro eeprom access status or phy access status when set, it indicates that the eeprom or phy access is in progress 6.13 eeprom & phy address register ( 0ch ) bit name default description 7:6 phy_adr ph01,rw phy address bit 1 and 0, the phy address bit [4:2] is force to 0. force to 01 in application. 5:0 eroa ph0,rw eeprom word address or phy register number. 6.14 eeprom & phy data register (ee_phy_l j 0dh ee_phy_h j 0eh) bit name default description 7:0 ee_phy_l ph0,rw eeprom or phy low byte data the low-byte data read from or write to eeprom or phy. 7:0 ee_phy_h ph0,rw eeprom or phy high byte data the high-byte data read from or write to eeprom or phy.
DM9008AEP ethernet controller with general processor interface preliminary 18 version: DM9008AEP-ds-p03 dec. 14, 2006 6.15 wake up control register ( 0fh ) (in 8-bit mode) bit name type description 7:6 reserved 0,ro reserved 5 linken p0,rw when set, it enables link status change wake up event this bit will not be affected after software reset 4 sampleen p0,rw when set, it enables sample frame wake up event this bit will not be affected after software reset 3 magicen p0,rw when set, it enables magic packet wake up event this bit will not be affected after software reset 2 linkst p0,ro when set, it indicates that link change and link status change event occurred this bit will not be affected after software reset 1 samplest p0,ro when set, it indicates that the sample frame is received and sample frame event occurred. this bit will not be affected after software reset 0 magicst p0,ro when set, indicates the magic packet is received and magic packet event occurred. this bit will not be affected after a software reset 6.16 physical address register ( 10h~15h ) bit name default description 7:0 pab5 e,rw physical address byte 5 (15h) 7:0 pab4 e,rw physical address byte 4 (14h) 7:0 pab3 e,rw physical address byte 3 (13h) 7:0 pab2 e,rw physical address byte 2 (12h) 7:0 pab1 e,rw physical address byte 1 (11h) 7:0 pab0 e,rw physical address byte 0 (10h) 6.17 multicast address register ( 16h~1dh ) bit name default description 7:0 mab7 x,rw multicast address byte 7 (1dh) 7:0 mab6 x,rw multicast address byte 6 (1ch) 7:0 mab5 x,rw multicast address byte 5 (1bh) 7:0 mab4 x,rw multicast address byte 4 (1ah) 7:0 mab3 x,rw multicast address byte 3 (19h) 7:0 mab2 x,rw multicast address byte 2 (18h) 7:0 mab1 x,rw multicast address byte 1 (17h) 7:0 mab0 x,rw multicast address byte 0 (16h) 6.18 general purpose control register ( 1eh ) (in 8-bit mode) bit name default description 7 reserved ph0,ro reserved 6:4 gpc64 ph, 111,ro general purpose control 6~4 define the input/output direction of pins gp6~4 respectively. these bits are all forced to ?1?s, so pins gp6~4 are output only. 3:1 gpc31 ph, 000,rw general purpose control 3~1 define the input/output direction of pins gp 3~1 respectively. when a bit is set 1, the direction of correspondent bit of general purpose register is output. other defaults are input 0 reserved ph1,ro reserved
DM9008AEP ethernet controller with general processor interface preliminary 19 version: DM9008AEP-ds-p03 dec. 14, 2006 6.19 general purpose register ( 1fh ) bit name default description 7 reserved 0,ro reserved 6-4 gpo ph0,rw general purpose output 6~4 (in 8-bit mode) these bits are reflect to pin gp6~4 respectively. 3:1 gpio ph0,rw general purpose (in 8-bit mode) when the correspondent bit of general purpose control register is 1, the value of the bit is reflected to pin gp3~1 respectively. when the correspondent bit of general purpose control register is 0, the value of the bit to be read is reflected from correspondent pins of gp3~1 respectively. 0 phypd 1,wo phy power down control 1: power down phy 0: power up phy 6.20 tx sram read pointer address register (22h~23h) bit name default description 7:0 trpah ps0,ro tx sram read pointer address high byte (23h) 7:0 trpal ps0.ro tx sram read pointer address low byte (22h) 6.21 rx sram write pointer address register (24h~25h) bit name default description 7:0 rwpah ps,0ch,ro rx sram write pointer address high byte (25h) 7:0 rwpal ps,00h.ro rx sram write pointer address low byte (24h) 6.22 vendor id register (28h~29h) bit name default description 7:0 vidh phe,0ah,ro vendor id high byte (29h) 7:0 vidl phe,46h.ro vendor id low byte (28h) 6.23 product id register (2ah~2bh) bit name default description 7:0 pidh phe,90h,ro product id high byte (2bh) 7:0 pidl phe,00h.ro product id low byte (2ah) 6.24 chip revision register (2ch) bit name default description 7:0 chipr p,19h,ro chip revision 6.25 transmit control register 2 ( 2dh ) bit name default description 7 led ph0,rw led mode when set, the led pins act as led mode 1. when cleared, the led mode is default mode 0 or depending eeprom setting. 6 rlcp ph0,rw retry late_collision packet re-transmit the packet with late-collision 5 dtu ph0,rw disable tx underrun retry disable to re-transmit the underruned packet
DM9008AEP ethernet controller with general processor interface preliminary 20 version: DM9008AEP-ds-p03 dec. 14, 2006 4 onepm ph0,rw one packet mode when set, only one packet transmit command can be issued before transmit completed. when cleared, at most two packet transmit command can be issued before transmit completed. 3~0 ifgs ph0,rw inter-frame gap setting 0xxx: 96-bit 1000: 64-bit 1001: 72-bit 1010:80-bit 1011:88-bit 1100:96-bit 1101:104-bit 1110: 112-bit 1111:120-bit 6.26 operation test control register ( 2eh ) bit name default description 7~6 scc ph0,rw system clock control set the internal system clock. 00: 50mhz 01: 20mhz 10: 100mhz 11: reserved 5 reserved ph0,rw reserved 4 soe ph0,rw internal sram output-enable always on 3 scs ph0,rw internal sram chip-select always on 2~0 phyop ph0,rw internal phy operation mode for testing 6.27 special mode control register ( 2fh ) bit name default description 7 sm_en ph0,rw special mode enable 6~3 reserved ph0,rw reserved 2 flc ph0,rw force late collision 1 fb1 ph0,rw force longest back-off time 0 fb0 ph0,rw force shortest back-off time
DM9008AEP ethernet controller with general processor interface preliminary 21 version: DM9008AEP-ds-p03 dec. 14, 2006 6.28 early transmit control/status register ( 30h ) bit name default description 7 ete hps0, rw early transmit enable enable bits[2:0] 6 ets2 hps0,ro early transmit status ii 5 ets1 hps0,ro early transmit status i 4~2 reserved 000,ro reserved 1~0 ett hps0,rw early transmit threshold start transmit when data write to tx fifo reach the byte-count threshold bit-1 bit-0 threshold ----- ---- ------------- 0 0 : 12.5% 0 1 : 25% 1 0 : 50% 1 1 : 75% 6.29 check sum control register ( 31h ) bit name default description 7~3 reserved 0,ro reserved 2 udpcse hps0,rw udp checksum generation enable 1 tcpcse hps0,rw tcp checksum generation enable 0 ipcse hps0,rw ip checksum generation enable 6.30 receive check sum status register ( 32h ) bit name default description 7 udps hps0,ro udp checksum status 1: checksum fail, if udp packet 6 tcps hps0,ro tcp checksum status 1: checksum fail, if tcp packet 5 ips hps0,ro ip checksum status 1: checksum fail, if ip packet 4 udpp hps0,ro udp packet 3 tcpp hps0,ro tcp packet 2 ipp hps0,ro ip packet 1 rcsen hps0,rw receive checksum checking enable when set, the checksum status (bit 7~2) will be stored in packet?s first byte(bit 7~2) of status header respectively. 0 dcse hps0,rw discard checksum error packet when set, if ip/tcp/udp checksum field is error, this packet will be discarded. 6.31 led pin control register ( 34h ) bit name default description 7:2 reserved ps0,ro reserved 1 gpio p0,rw led act as general purpose signals in 16-bit mode 1: pin 38/39 (led2/1) act as the general purpose pins that are controlled by registers 1eh bit 2/1 and 1fh bit 2/1 respectively.
DM9008AEP ethernet controller with general processor interface preliminary 22 version: DM9008AEP-ds-p03 dec. 14, 2006 0 mii p0,rw led act as smi signals in 16-bit mode 1: pin 38/39 (led2/1) act as the mii management interface mode. in this mode, the led1 act as data (mdio) signal and the led2 act as sourced clock (mdc) signal. these two pin are controlled by registers 0bh,0ch, and 0dh. 6.32 processor bus control register ( 38h ) bit name default description 7:5 curr p011,ro data bus current driving/sinking capability 000: 2ma 001: 4ma 010: 6ma 011: 8ma (default) 100: 10ma 101: 12ma 110: 14ma 111: 16ma 4 reserved p0,rw reserved 3 gpio p0,rw enable schmitt trigger 1: pin 35/36/37 (ior/iow/cs#) have schmitt trigger capability. 2 reserved p0,rw reserved 1 iow_spike p0,rw eliminate iow spike 1: eliminate about 2ns iow spike 0 ior_spike p1,rw eliminate ior spike 1: eliminate about 2ns ior spike
DM9008AEP ethernet controller with general processor interface preliminary 23 version: DM9008AEP-ds-p03 dec. 14, 2006 6.33 int pin control register ( 39h ) bit name default description 7:2 reserved ps0,ro reserved 1 int_type pet0,rw int pin output type control 1: int open-collector output 0: int direct output 0 int_pol pet0,rw int pin polarity control 1: int active low 0: int active high 6.34 system clock turn on control register ( 50h ) bit name default description 7:1 reserved - reserved 0 dis_clk p0,w stop internal system clock 1: internal system clock turn off, internal phyceiver also power down 0: internal system clock is on 6.35 resume system clock control register ( 51h ) when the index port set to 51h, the internal system clock is turn on.
DM9008AEP ethernet controller with general processor interface preliminary 24 version: DM9008AEP-ds-p03 dec. 14, 2006 6.36 memory data pre-fetch read command without address increment register (f0h) bit name default description 7:0 mrcmdx x,ro read data from rx sram. after the read of this command, the read pointer of internal sram is unchanged. and the dm9008a starts to pre-fetch the sram data to internal data buffers. 6.37 memory data read command without address increment register (f1h) bit name default description 7:0 mrcmdx1 x,ro read data from rx sram. after the read of this command, the read pointer of internal sram is unchanged 6.38 memory data read command with address increment register (f2h) bit name default description 7:0 mrcmd x,ro read data from rx sram. after the read of this command, the read pointer is increased by 1or 2 depends on the operator mode (8-bit or16-bit respectively) 6.39 memory data read_address register (f4h~f5h) bit name default description 7:0 mdrah phs0,rw memory data read_ address high byte. it will be set to 0ch, when imr bit7 =1 7:0 mdral phs0,rw memory data read_ address low byte 6.40 memory data write command without address increment register (f6h) bit name default description 7:0 mwcmdx x,wo write data to tx sram. after the write of this command, the write pointer is unchanged 6.41 memory data write command with address increment register (f8h) bit name default description 7:0 mwcmd x,wo write data to tx sram after the write of this command, the write pointer is increased by 1 or 2, depends on the operator mode. (8-bit or 16-bit respectively) 6.42 memory data write_address register (fah~fbh) bit name default description 7:0 mdrah phs0,rw memory data write_ address high byte 7:0 mdral phs0,rw memory data write_ address low byte 6.43 tx packet length register (fch~fdh) bit name default description 7:0 txplh x,r/w tx packet length high byte 7:0 txpll x,,r/w tx packet length low byte
DM9008AEP ethernet controller with general processor interface preliminary 25 version: DM9008AEP-ds-p03 dec. 14, 2006 6.44 interrupt status register (feh) bit name default description 7 iomode t0, ro 0 : 16-bit mode 1: 8-bit mode 6 reserved ro reserved 5 lnkchg phs0,rw/c1 link status change 4 udrun phs0,rw/c1 transmit underrun 3 roo phs0,rw/c1 receive overflow counter overflow 2 ro phs0,rw/c1 receive overflow 1 pt phs0,rw/c1 packet transmitted 0 pr phs0,rw/c1 packet received 6.45 interrupt mask register (ffh) bit name default description 7 par hps0,rw enable the sram read/write pointer to automatically return to the start address when pointer addresses are over the sram size. driver needs to set. when driver sets this bit, reg_f5 will set to 0ch automatically 6 reserved ro reserved 5 lnkchgi phs0,rw enable link status change interrupt 4 udruni phs0,rw enable transmit underrun interrupt 3 rooi phs0,rw enable receive overflow counter overflow interrupt 2 roi phs0,rw enable receive overflow interrupt 1 pti phs0,rw enable packet transmitted interrupt 0 pri phs0,rw enable packet received interrupt
DM9008AEP ethernet controller with general processor interface preliminary 26 version: DM9008AEP-ds-p03 dec. 14, 2006 7. eeprom format name word offset description mac address 0 0~5 6 byte ethernet address auto load control 3 6-7 bit 1:0=01: update vendor id and product id bit 3:2=01: accept setting of word6 [8:0] bit 5:4=01: reserved bit 7:6=01: accept setting of word7 [3:0] (in 8-bit mode) bit 9:8=01: reserved bit 11:10=01: accept setting of word7 [7] bit 13:12=01: accept setting of word7 [8] bit 15:14=01: accept setting of word7 [15:12] vendor id 4 8-9 2 byte vendor id (default: 0a46h) product id 5 10-11 2 byte product id (default: 9000h) pin control 6 12-13 when word 3 bit [3:2]=01, these bits can control the cs#, ior#, iow# and int pins polarity. bit0: cs# pin is active low when set (default active low) bit1: ior# pin is active low when set (default: active low) bit2: iow# pin is active low when set (default: active low) bit3: int pin is active low when set (default: active high) bit4: int pin is open-collected (default: force output) bit 15:5: reserved wake-up mode control 7 14-15 bit0: the wakeup pin is active low when set (default: active high) bit1: the wakeup pin is in pulse mode when set (default: level mode) bit2: magic wakeup event is enabled when set. (default: disable) bit3: link_change wakeup event is enabled when set (default: disable) bit6:4: reserved bit7: led mode 1 (default: 0) bit8: internal phy is enabled after power-on (default: disable) bit11:9: reserved bit13:12: 01 = led2 act as iowait in 16-bit mode bit13:12: 10 = led2 act as wake in 16-bit mode bit14: 1: hp auto-mdix on, 0: hp auto-mdix off(default on) bit 15: led1 act as io16 in 16-bit mode
DM9008AEP ethernet controller with general processor interface preliminary 27 version: DM9008AEP-ds-p03 dec. 14, 2006 8. mii register description add name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset loop back speed select auto-n enable power down isolate restart auto-n full duplex coll. test reserved 00 contr ol 0 0 1 1 0 0 0 1 0 000_0000 t4 cap. tx fdx cap. tx hdx cap. 10 fdx cap. 10 hdx cap. reserved pream. supr. auto-n compl. remote fault auto-n cap. link status jabber detect extd cap. 01 status 0 1 1 1 1 0000 1 0 0 1 0 0 1 02 phyid1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 phyid2 1 0 1 1 1 0 model no. version no. 03 01010 0000 04 auto-neg. advertise next page flp rcv ack remote fault reserved fc adv t4 adv tx fdx adv tx hdx adv 10 fdx adv 10 hdx adv advertised protocol selector field 05 link part. ability lp next page lp ack lp rf reserved lp fc lp t4 lp tx fdx lp tx hdx lp 10 fdx lp 10 hdx link partner protocol selector field 06 auto-neg. expansio n reserved pardet fault lp next pg able next pg able new pg rcv lp auton cap. 16 specifie d config. reserved rpdctr -en reset st. mch pream. supr. sleep mode remote loopout 17 specifie d conf/stat reversed phy addr [4:0] auto-n. monitor bit [3:0] 18 10t conf/stat rsvd lp enable hbe enable sque enable jab enable reserve d reserved polarity reverse key to default in the register description that follows, the default column takes the form: , / where j : 1 bit set to logic one 0 bit set to logic zero x no default value : ro = read only rw = read/write : sc = self clearing p = value permanently set ll = latching low lh = latching high 8.1 basic mode control register (bmcr) - 00 bit bit name default description 0.15 reset 0, rw/sc reset 1=software reset 0=normal operation this bit sets the status and controls the phy registers to their default states. this bit, which is self-clearing, will keep
DM9008AEP ethernet controller with general processor interface preliminary 28 version: DM9008AEP-ds-p03 dec. 14, 2006 returning a value of one until the reset process is completed 0.14 loopback 0, rw loopback loop-back control register 1 = loop-back enabled 0 = normal operation 0.13 speed selection 1, rw speed select 1 = 100mbps 0 = 10mbps link speed may be selected either by this bit or by auto-negotiation. when auto-negotiation is enabled and bit 12 is set, this bit will return auto-negotiation selected medium type 0.12 auto-negotiatio n enable 1, rw auto-negotiation enable 1 = auto-negotiation is enable d, bit 8 and 13 will be in auto-negotiation status 0.11 power down 0, rw power down while in the power-down state, the phy should respond to management transactions. during the transition to power-down state and while in the power-down state, the phy should not generate spurious signals on the mii 1=power down 0=normal operation 0.10 isolate 0,rw isolate force to 0 in application. 0.9 restart auto-negotiation 0,rw/sc restart auto-negotiation 1 = restart auto-negotiation. re -initiates the auto-negotiation process. when auto-n egotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. this bit is self-clearing and it will keep returning to a value of 1 until auto -negotiation is init iated by the dm9008a. the operation of the auto-negotiation process will not be affected by the management entity that clears this bit 0 = normal operation 0.8 duplex mode 1,rw duplex mode 1 = full duplex operation. duplex selection is allowed when auto-negotiation is disabled (bit 12 of this register is cleared). with auto-negotiation enabled, this bit reflects the duplex capability selected by auto-negotiation 0 = normal operation 0.7 collision test 0,rw collision test 1 = collision test enabled. when set, this bit will cause the col signal to be asserted in response to the assertion of tx_en in internal mii interface.
DM9008AEP ethernet controller with general processor interface preliminary 29 version: DM9008AEP-ds-p03 dec. 14, 2006 0 = normal operation 0.6-0.0 reserved 0,ro reserved read as 0, ignore on write 8.2 basic mode status register (bmsr) - 01 bit bit name default description 1.15 100base-t4 0,ro/p 100base-t4 capable the dm9008a is not support 100base-t4 mode. 1.14 100base-tx full-duplex 1,ro/p 100base-tx full duplex capable the dm9008a is not support 100base-tx full duplex mode. 1.13 100base-tx half-duplex 1,ro/p 100base-tx half duplex capable the dm9008a is not support 100base-tx half duplex mode 1.12 10base-t full-duplex 1,ro/p 10base-t full duplex capable 1 = dm9008a is able to perform 10base-t in full duplex mode 0 = dm9008a is not able to perform 10base-tx in full duplex mode 1.11 10base-t half-duplex 1,ro/p 10base-t half duplex capable 1 = dm9008a is able to perform 10base-t in half duplex mode 0 = dm9008a is not able to perform 10base-t in half duplex mode 1.10-1.7 reserved 0,ro reserved read as 0, ignore on write 1.6 mf preamble suppression 1,ro mii frame preamble suppression 1 = phy will accept management frames with preamble suppressed 0 = phy will not accept management frames with preamble suppressed 1.5 auto-negotiation complete 0,ro auto-negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 1.4 remote fault 0, ro/lh remote fault 1 = remote fault condition detect ed (cleared on read or by a chip reset). fault criteria and detection method is dm9008a implementation specific. this bit will set after the rf bit in the anlpar (bit 13, register address 05) is set 0 = no remote fault condition detected 1.3 auto-negotiation ability 1,ro/p auto conf iguration ability 1 = dm9008a is able to perform auto-negotiation 0 = dm9008a is not able to perform auto-negotiation
DM9008AEP ethernet controller with general processor interface preliminary 30 version: DM9008AEP-ds-p03 dec. 14, 2006 1.2 link status 0,ro/ll link status 1 = valid link is established 0 = link is not established the link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the link status bit to be cleared and remain cleared until it is read via the management interface 1.1 jabber detect 0, ro/lh jabber detect 1 = jabber condition detected 0 = no jabber this bit is implemented with a latching function. jabber conditions will set this bit unless it is cleared by a read to this register through a management interface or a dm9008a reset. 1.0 extended capability 1,ro/p extended capability 1 = extended register capable 0 = basic register capable only 8.3 phy id identifier register #1 (phyid1) - 02 the phy identifier registers #1 and #2 work together in a single identifier of the dm9008a. the identifier consists of a concatenation of the organizationally unique identifier (oui), a vendor's model number, and a model revision number. davicom semiconductor's ieee assigned oui is 00606e. bit bit name default description 2.15-2.0 oui_msb <0181h> oui most significant bits this register stores bit 3 to 18 of the oui (00606e) to bit 15 to 0 of this register respectively. the most significant two b its of the oui are ignored (the ieee standard refers to these as bit 1 and 2) 8.4 phy id identifier register #2 (phyid2) - 03 bit bit name default description 3.15-3.1 0 oui_lsb <101110>, ro/p oui least significant bits bit 19 to 24 of the oui (00606e) are mapped to bit 15 to 10 of this register respectively 3.9-3.4 vndr_mdl <001010>, ro/p vendor model number five bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit 9) 3.3-3.0 mdl_rev <0000>, ro/p model revision number five bits of vendor model revision number mapped to bit 3 to 0 (most significant bit to bit 4)
DM9008AEP ethernet controller with general processor interface preliminary 31 version: DM9008AEP-ds-p03 dec. 14, 2006 8.5 auto-negotiation advertisement register (anar) - 04 this register contains the advertised abilities of this dm9008a device as they will be transmitted to its link partner during auto-negotiation. bit bit name default description 4.15 np 0,ro/p next page indication 0 = no next page available 1 = next page available the dm9008a has no next page, so this bit is permanently set to 0 4.14 ack 0,ro acknowledge 1 = link partner ability data reception acknowledged 0 = not acknowledged the dm9008a's auto-negotiation state machine will automatically control this bit in the outgoing flp bursts and set it at the appropriate time during the auto-negotiation process. software should not attempt to write to this bit. 4.13 rf 0, rw remote fault 1 = local device senses a fault condition 0 = no fault detected 4.12-4.1 1 reserved x, rw reserved write as 0, ignore on read 4.10 fcs 0, rw flow control support 1 = controller chip supports flow control ability 0 = controller chip doesn ? t support flow control ability 4.9 t4 0, ro/p 100base-t4 support 100base-t4 is not supported by dm9008a. 4.8 tx_fdx 1, rw 100base-tx full duplex support 100base-tx full duplex is not supported by dm9008a. 4.7 tx_hdx 1, rw 100base-tx support 100base-tx half duplex is not supported by dm9008a. 4.6 10_fdx 1, rw 10base-t full duplex support 1 = 10base-t full duplex is supported by the local device 0 = 10base-t full duplex is not supported 4.5 10_hdx 1, rw 10base-t support 1 = 10base-t half duplex is supported by the local device 0 = 10base-t half duplex is not supported 4.4-4.0 selector <00001>, rw protocol selection bits these bits contain the binary encoded protocol selector supported by this node <00001> indicates that this device supports ieee 802.3 csma/cd
DM9008AEP ethernet controller with general processor interface preliminary 32 version: DM9008AEP-ds-p03 dec. 14, 2006 8.6 auto-negotiation link partner ability register (anlpar) ? 05 this register contains the advertised abiliti es of the link partner when received during auto-negotiation. bit bit name default description 5.15 np 0, ro next page indication 0 = link partner, no next page available 1 = link partner, next page available 5.14 ack 0, ro acknowledge 1 = link partner ability data reception acknowledged 0 = not acknowledged the dm9008a's auto-negotiation state machine will automatically control this bi t from the incoming flp bursts. software should not attempt to write to this bit 5.13 rf 0, ro remote fault 1 = remote fault indicated by link partner 0 = no remote fault indicated by link partner 5.12-5.1 1 reserved 0, ro reserved read as 0, ignore on write 5.10 fcs 0, ro flow control support 1 = controller chip supports flow control ability by link partner 0 = controller chip doesn ? t support flow control ability by link partner 5.9 t4 0, ro 100base-t4 support 1 = 100base-t4 is supported by the link partner 0 = 100base-t4 is not supported by the link partner 5.8 tx_fdx 0, ro 100base-tx full duplex support 1 = 100base-tx full duplex is supported by the link partner 0 = 100base-tx full duplex is not supported by the link partner 5.7 tx_hdx 0, ro 100base-tx support 1 = 100base-tx half duplex is supported by the link partner 0 = 100base-tx half duplex is not supported by the link partner 5.6 10_fdx 0, ro 10base-t full duplex support 1 = 10base-t full duplex is supported by the link partner 0 = 10base-t full duplex is not supported by the link partner 5.5 10_hdx 0, ro 10base-t support 1 = 10base-t half duplex is supported by the link partner 0 = 10base-t half duplex is not supported by the link
DM9008AEP ethernet controller with general processor interface preliminary 33 version: DM9008AEP-ds-p03 dec. 14, 2006 partner 5.4-5.0 selector <00000>, ro protocol selection bits link partner ? s binary encoded protocol selector 8.7 auto-negotiation expansion register (aner)- 06 bit bit name default description 6.15-6.5 reserved 0, ro reserved read as 0, ignore on write 6.4 pdf 0, ro/lh local device parallel detection fault pdf = 1: a fault detected via parallel detection function. pdf = 0: no fault detected via parallel detection function 6.3 lp_np_abl e 0, ro link partner next page able lp_np_able = 1: link partner, next page available lp_np_able = 0: link partner, no next page 6.2 np_able 0,ro/p local device next page able np_able = 1: dm9008a, next page available np_able = 0: dm9008a, no next page dm9008a does not support this function, so this bit is always 0 6.1 page_rx 0, ro/lh new page received a new link code word page received. this bit will be automatically cleared when the register (register 6) is read by management 6.0 lp_an_abl e 0, ro link partner auto-negotiation able a ? 1 ? in this bit indicates that the link partner supports auto-negotiation 8.8 davicom specified configuration register (dscr) ? 16 bit bit name default description 16.15 bp_4b5b 0,rw bypass 4b5b encoding and 5b4b decoding 1 = 4b5b encoder and 5b4b decoder function bypassed 0 = normal 4b5b and 5b4b operation 16.14 bp_scr 0, rw bypass scrambler/descrambler function 1 = scrambler and descrambler function bypassed 0 = normal scrambler and descrambler operation 16.13 bp_align 0, rw bypass symbol alignment function 1 = receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. transmit functions (symbol encoder and scrambler) bypassed
DM9008AEP ethernet controller with general processor interface preliminary 34 version: DM9008AEP-ds-p03 dec. 14, 2006 0 = normal operation 16.12 bp_adpok 0, rw bypass adpok force signal detector (sd) active. this register is for debug only, not release to customer 1=forced sd is ok, 0=normal operation 16.11 reserved 0, rw reserved force to 0 in application. 16.10 tx/fx 1, rw 100base-tx/fx mode control 1 = 100base-tx operation 0 = 100base-fx operation 16.9 reserved 0, ro reserved 16.8 reserved 0, rw reserved force to 0 in application. 16.7 f_link_100 0, rw force good link in 100mbps 0 = normal 100mbps operation 1 = force 100mbps good link status this bit is useful for diagnostic purposes 16.6 spled_ctl 0, rw reserved force to 0 in application. 16.5 colled_ct l 0, rw reserved force to 0 in application. 16.4 rpdctr-en 1, rw reduced power down control enable this bit is used to enable automatic reduced power down 0 = disable automatic reduced power down 1 = enable automatic reduced power down 16.3 smrst 0, rw reset state machine when writes 1 to this bit, all state machines of phy will be reset. this bit is self-cle ar after reset is completed 16.2 mfpsc 1, rw mf preamble suppression control frame preamble suppression control bit 1 = mf preamble suppression bit on 0 = mf preamble suppression bit off
DM9008AEP ethernet controller with general processor interface preliminary 35 version: DM9008AEP-ds-p03 dec. 14, 2006 16.1 sleep 0, rw sleep mode writing a 1 to this bit will cause phy entering the sleep mode and power down all circuit except oscillator and clock generator circuit. when waking up from sleep mode (write this bit to 0), the configura tion will go back to the state before sleep; but the state machine will be reset 16.0 rlout 0, rw remote loopout control when this bit is set to 1, the re ceived data will loop out to the transmit channel. this is usef ul for bit error rate testing 8.9 davicom specified configuration and status register (dscsr) - 17 bit bit name default description 17.15- 17.12 reserv ed 1111, ro reserved 17.11- 17.9 reserved 0, ro reserved read as 0, ignore on write 17.8- 17.4 phyadr [4:0] (phyadr), rw phy address bit 4:0 the first phy address bit transmitted or received is the msb of the address (bit 4). a station management entity connected to multiple phy entities must know the appropriate address of each phy 17.3- 17.0 anmb[3: 0] 0, ro auto-negotiation monitor bits these bits are for debug only. the auto-negotiation status will be written to these bits. b3 b2 b1 b0 0 0 0 0 in idle state 0 0 0 1 ability match 0 0 1 0 acknowledge match 0 0 1 1 acknowledge match fail 0 1 0 0 consistency match 0 1 0 1 consistency match fail 0 1 1 0 parallel detects signal_link_ready 0 1 1 1 parallel detects signal_link_ready fail
DM9008AEP ethernet controller with general processor interface preliminary 36 version: DM9008AEP-ds-p03 dec. 14, 2006 8.10 10base-t configuration/status (10btcsr) - 18 bit bit name default description 18.15 reserved 0, ro reserved read as 0, ignore on write 18.14 lp_en 1, rw link pulse enable 1 = transmission of link pulses enabled 0 = link pulses disabled, good link condition forced this bit is valid only in 10mbps operation 18.13 hbe 1,rw heartbeat enable 1 = heartbeat function enabled 0 = heartbeat function disabled when the dm9008a is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode) 18.12 squelch 1, rw squelch enable 1 = normal squelch 0 = low squelch 18.11 jaben 1, rw jabber enable enables or disables the jabber function when the dm9008a is in 10base-t full duplex or 10base-t transceiver loopback mode 1 = jabber function enabled 0 = jabber function disabled 18.10 reserved 0, rw reserved force to 0, in application. 18.9- 18.1 reserved 0, ro reserved read as 0, ignore on write 18.0 polr 0, ro polarity reversed when this bit is set to 1, it indicates that the 10mbps cable polarity is reversed. this bit is automatically set and cleared by 10base-t module 8.11 (specified config) register ? 20 bit bit name default description 20.15 tstse1 0,rw vendor test select control 20.14 tstse2 0,rw vendor test select control 20.13 force_txsd 0,rw force signal detect 1: force sd signal ok in 100m
DM9008AEP ethernet controller with general processor interface preliminary 37 version: DM9008AEP-ds-p03 dec. 14, 2006 0: normal sd signal. 20.12 force_fef 0,rw vendor test select control 20.11-20 .8 reserved 0, ro reserved read as 0, ignore on write 20.7 mdix_cntl mdi/mdix, ro the polarity of mdi/mdix value 1: mdix mode 0: mdi mode 20.6 autoneg_lpbk 0,rw auto-negotiation loopback 1: test internal digital auto-negotiation loopback 0: normal. 20.5 mdix_fix value 0, rw mdix_cntl force value: when mdix_down = 1, mdix_cntl value depend on the register value. 20.4 mdix_down 0,rw hp auto-mdix down manual force mdi/mdix. 0: enable hp auto-mdix 1: disable hp auto-mdix , mdix_cntl value depend on 20.5 20.3 monsel1 0,rw vendor monitor select 20.2 monsel0 0,rw vendor monitor select 20.1 reserved 0,rw reserved force to 0, in application. 20.0 pd_value 0,rw power down control value decision the value of each field register 19. 1: power down 0: normal
DM9008AEP ethernet controller with general processor interface preliminary 38 version: DM9008AEP-ds-p03 dec. 14, 2006 9. functional description 9.1 host interface the host interface is a general processor local bus that using chip select (pin cs#) to access dm9008a. pin cs# is default low active which can be re-defined by eeprom setting. there are only two addressing ports through the access of the host interface. one port is the index port and the other is the data port. the index port is decoded by the pin cmd =0 and the data port by the pin cmd =1. the contents of the index port are the register address of the data port. before the access of any register, the address of the register must be saved in the index port. 9.2 direct memory access control the dm9008a provides dma capability to simplify the access of the internal memory. after the programming of the starting address of the internal memory and then issuing a dummy read/write command to load the current data to internal data buffer, the desired location of the internal memory can be accessed by the read/write command registers. the memory?s address will be increased with the size that equals to the current operation mode (i.e. the 8-bit or 16-bit mode) and the data of the next location will be loaded into internal data buffer automatically. it is noted that the data of the first access (the dummy re ad/write command) in a sequential burst should be ignored because that the data was the contents of the last read/write command. the internal memory size is 16k bytes. the first location of 3k bytes is used for the data buffer of the packet transmission. the other 13k bytes are used for the buffer of the receiving packets. so in the write memory operation, when the bit 7 of imr is set, the memory address increment w ill wrap to location 0 if the end of address (i.e. 3k) is reached. in a similar way, in the read memory operation, when the bit 7 of imr is set, the memory address increment will wrap to location 0x0c00 if the end of address (i.e. 16k) is reached. 9.3 packet transmission there are two packets, sequentially named as index i and index ii, can be stored in the tx sram at the same time. the index register 02h controls the insertion of crc and pads. their statuses are recorded at index registers 03h and 04h respectively. the start address of transmission is 00h and the current packet is index i after software or hardware reset. firstly write data to the tx sram using the dma port and then write the byte count to byte_ count register at index register 0fch and 0fdh. set the bit 1 of control register. the dm9008a starts to transmit the index i packet. before the transmission of the index i packet ends, the data of the next (index ii) packet can be moved to tx sram. after the index i packet ends the transmission, write the byte count data of the index ii to byte_count register and then set the bit 1 of control register to transmit the index ii packet. the following packets, named index i, ii, i, ii,?, use the same way to be transmitted. 9.4 packet reception the rx sram is a ring data structure. the start address of rx sram is 0c00h after software or hardware reset. each packet has a 4-byte header followed with the data of the reception packet which crc field is included. the format of the 4-byte header is 01h, status, byte_count low, and byte_count high. it is noted that the start address of each packet is in the proper address boundary which depends on the operation mode (the 8-bit or 16-bit ).
DM9008AEP ethernet controller with general processor interface preliminary 39 version: DM9008AEP-ds-p03 dec. 14, 2006 9.5 10base-t operation the 10base-t transceiver is ieee 802.3 compliant. when the dm9008a is operating in 10base-t mode, the coding scheme is manchester. data processed for transmit is presented to the mii interface in nibble format, converted to a serial bit stream, then the manchester encoded. when receiving, the bit stream, encoded by the manchester, is decoded and converted into nibble format to present to the mii interface. 9.6 collision detection for half-duplex operation, a collision is detected when the transmit and receive channels are active simultaneously. when a collision is detected, it will be reported by the col signal on the mii interface. collision detection is disabled in full duplex operation. 9.7 carrier sense carrier sense (crs) is asserted in half-duplex operation during transmission or reception of data. during full-duplex mode, crs is asserted only during receive operations. 9.8 auto-negotiation the objective of auto-negotiation is to provide a means to exchange information between linked devices and to automatically configure both devices to take maximum advantage of their abilities. it is important to note that auto-negotiation does not test the characteristics of the linked segment. the auto-negotiation function provides a means for a device to advertise supported modes of operation to a remote link partner, acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes of operation. this allows devices on both ends of a segment to establish a link at the best common mode of operation. if more than one common mode exists between the two devices, a mechanism is provided to allow the devices to resolve to a single mode of operation using a predetermined priority resolution function. auto-negotiation also provides a parallel detection function for devices that do not support the auto-negotiation feature. during parallel detection there is no exchange of information of configuration. instead, the receive signal is examined. if it is discovered that the signal matches a technology, which the receiving device supports, a connection will be automatically established using that technology. this allows devices not to support auto-negotiation but support a common mode of operation to establish a link.
DM9008AEP ethernet controller with general processor interface preliminary 40 version: DM9008AEP-ds-p03 dec. 14, 2006 9.9 power reduced mode the signal detect circuit is always turned to monitor whether there is any signal on the media (cable disconnected). the dm9008a automatically turns off the power and enters the power reduced mode, whether its operation mode is n-way or force mode. when enters the power reduced mode, the transmit circuit still sends out fast link pules with minimum power consumption. if a valid signal is detected from the media the device will wake up and resume a normal operation mode. that can be writing zero to phy reg. 16.4 to disable power reduced mode. 9.9.1 power down mode the phy reg.0.11 can be set high to enter the power down mode, which disables all transmit, receive functions, except the mii management interface. 9.9.2 reduced transmit power mode the additional transmit power reduction can be gained by designing with 1.25:1 turns ration magnetic on its tx side and using a 8.5k ? resistor on bgres and agnd pins, and the txo+/txo- pulled high resistors should be changed from 50 ? to 78 ? . this configuration could be reduced about 20% transmit power.
DM9008AEP ethernet controller with general processor interface preliminary 41 version: DM9008AEP-ds-p03 dec. 14, 2006 10. dc and ac electrical characteristics 10.1 absolute maximum ratings ( 25 c ) symbol parameter min. max. unit conditions d vdd supply voltage -0.3 3.6 v v in dc input voltage (vin) -0.5 5.5 v v out dc output voltage(vout) -0.3 3.6 v tstg storage temperature range -65 +150
tc case temperature 0 +85
ast "j
ta ambient temperature 0 +70
lt lead temperature (tl,soldering,10 sec.). ? +235
10.1.1 operating conditions symbol parameter min. max. unit conditions d vdd supply voltage 3.135 3.465 v tc case reserve --- 85 c 10base-t tx (100% utilization) --- 92 ma 3.3v 10base-t idle --- 38 ma 3.3v auto-negotiation --- 56 ma 3.3v power reduced mode(withou t cable) --- 31 ma 3.3v power down mode --- 21 ma 3.3v power down mode (system clock off) --- 7 ma 3.3v 10.2 dc electrical characteristics (vdd = 3.3v) symbol parameter min. typ. max. unit conditions inputs v il input low voltage - - 0.8 v v ih input high voltage 2.0 - - v i il input low leakage current -1 - - ua vin = 0.0v i ih input high leakage current - - 1 ua vin = 3.3v outputs v ol output low voltage - - 0.4 v iol = 4ma v oh output high voltage 2.4 - - v ioh = -4ma receiver v icm rx+/rx- common mode input voltage - 2.5 - v 100 ? termination across transmitter v td10 10tx+/- differential output voltage 4.4 5 5.6 v peak to peak i td10 10tx+/- differential output current 44 50 56 ma absolute value
DM9008AEP ethernet controller with general processor interface preliminary 42 version: DM9008AEP-ds-p03 dec. 14, 2006 10.3 ac electrical characteristics & timing waveforms 10.3.1 oscillator/crystal timing symbol parameter min. typ. max. unit conditions t ckc osc clock cycle 39.998 40 40.002 ns 50ppm t pwh osc pulse width high 16 20 24 ns t pwl osc pulse width low 16 20 24 ns 10.3.2 processor i/o read timing t5 t1 t2 t6 ior# sd ? ? ? ? t4 t3 ? ? cs#, cm d io16 t8 ? t7 ? symbol parameter min. typ. max. unit t 1 cs#,cmd valid to ior# valid 0 ns t 2 ior# width 10 ns t 3 system data(sd) delay time 3 ns t 4 ior# invalid to system data(sd) invalid 3 ns t 5 ior# invalid to cs#,cmd invalid 0 ns t 6 ior# invalid to next ior#/iow# valid when read dm9008a register 2 clk* t 6 ior# invalid to next ior#/iow# valid when read dm9008a memory with f0h register 4 clk* t 2 +t 6 ior# invalid to next ior#/iow# valid when read dm9008a memory with f2h register 1 clk* t 7 cs#,cmd valid to io16 valid 3 ns t 8 cs#,cmd invalid to io16 invalid 3 ns *note j (the default clk period is 20ns) 1. the io16 is valid when the sd bus width is 16-bit and the system address is data port (i.e. cmd is high) and the value of index port is memory data register index. ? ex. f0h, f2h, f6h or f8h ?
DM9008AEP ethernet controller with general processor interface preliminary 43 version: DM9008AEP-ds-p03 dec. 14, 2006 10.4.3 processor i/o write timing t1 t4 cs# , cmd ? t6 ? ? iow# t2 ? sd ? t3 t8 t7 ? ? io16 ? t5 symbol parameter min. typ. max. unit t 1 cs#,cmd valid to iow# valid 0 ns t 2 iow# width 10 ns t 3 system data(sd) setup time 10 ns t 4 system data(sd) hold time 3 ns t 5 iow# invalid to cs#,cmd invalid 0 ns t 6 iow# invalid to next iow#/ior# valid when write dm9008a index port 1 clk* t 6 iow# invalid to next iow#/ior# valid when write dm9008a data port 2 clk* t 2 +t 6 iow# invalid to next iow#/ior# valid when write dm9008a memory 1 clk* t 7 cs#,cmd valid to io16 valid 3 ns t 8 cs#,cmd invalid to io16 invalid 3 ns note j (the default clk period is 20ns) 1. the io16 is valid when the sd bus width is 16-bit and system address is data port (i.e. cmd is high) and the value of index port is memory data register index (ex. f0h, f2h, f6h or f8h ?
DM9008AEP ethernet controller with general processor interface preliminary 44 version: DM9008AEP-ds-p03 dec. 14, 2006 10.4.4 eeprom interface timing &&$4 &&$, &&%*0 5 5 5 5 5 5 5 symbol parameter min. typ. max. unit t 1 eeck frequency 0.375 mhz t2 eecs setup time 500 ns t 3 eecs hold time 2166 ns t 4 eedio setup time when output 480 ns t5 eedio hold time when output 2200 ns t 6 eedio setup time when input 8 ns t 7 eedio hold time when input 8 ns
DM9008AEP ethernet controller with general processor interface preliminary 45 version: DM9008AEP-ds-p03 dec. 14, 2006 11. application notes 11.1 network interface signal routing place the transformer as close as possible to the rj-45 connector. place all the 50 ? resistors as close as possible to the dm9008a rxi ? and txo ? pins. traces routed from rxi ? and txo ? to the transformer should run in close pairs directly to the transformer. the designer should be careful not to cross the transmit and receive pairs. as always, vias should be avoided as much as possible. the network interface should be void of any signals other than the txo ? and rxi ? pairs between the rj-45 to the transformer and the transformer to the dm9008a.. there should be no power or ground planes in the area under the network side of the transformer to include the area under the rj-45 connector. keep chassis ground away from all active signals. the rj-45 connector and any unused pins should be tied to chassis ground through a resistor divider network and a 2kv bypass capacitor. the band gap resistor should be placed as physically close as pins 1 and 48 as possible (refer to figure 11-1 and 11-2). the designer should not run any high-speed signal near the band gap resistor placement. hp auto-mdix application figure 11-1 hp auto-mdix
DM9008AEP ethernet controller with general processor interface preliminary 46 version: DM9008AEP-ds-p03 dec. 14, 2006 11.3 non hp auto-mdix transformer application figure 11-2 non hp auto-mdix 11.4 power decoupling capacitors davicom semiconductor recommends placing all the decoupling capacitors for all power supply pins as close as possible to the power pads of the dm9008a (the best placed distance is < 3mm from pin). the recommended decoupling capacitor is 0.1 ? f or 0.01 ? f, as required by the design layout.
DM9008AEP ethernet controller with general processor interface preliminary 47 version: DM9008AEP-ds-p03 dec. 14, 2006 11.41 dm9008a + dm8606a circuit dm8606af + dm9008a 1.0 davicom semiconductor inc. 01 tuesday , april 11, 2006 title size document number rev date: sheet of dgnd dvdd_33 agnd dgnd dvdd_33 dgnd dgnd dvdd_33 avdd_25 dgnd dgnd agnd dvdd_33 dvdd_33 dvdd_33 dgnd dgnd dgnd dgnd avdd_18 agnd dvdd_33 agnd agnd dvdd_33 dgnd dgnd agnd avdd_18 avdd_33 dvdd_33 agnd dgnd agnd agnd agnd dvdd_18 dvdd_33 dvdd_33 agnd dgnd dvdd_33 agnd agnd avdd_33 dvdd_18 dvdd_33 dgnd avdd_18 avdd_18 agnd dvdd_33 dvdd_33 dvdd_33 agnd avdd_33 dgnd dvdd_33 dvdd_5 dvdd_33 dvdd_33 md c p2_l/a_led p1_rx- p4_fx control p2_rx+ p0_l/a_led p0_tx+ p3_dupcol p2_tx+ p3_tx+ p1_tx+ p1_l/a_led p4_tx+ p4_rx- p2_tx- p0_tx- p4_tx- p2_rx- md i o p1_tx- p4_l/a_led p1_rx+ p0_rx+ vref p4_rx+ p3_rx- rtx p3_rx+ p4_ldspd p3_l/a_led p3_tx- p0_rx- p3_ldspd p4_dupcol sd9 tx- tx+ ior# sd6 mii_mdc int sd1 sd11 iow# sd8 mii_mdio sd10 sd12 sd7 sd15 cmd rx+ sd13 rx- rst# p3_tx- p3_tx+ p3_rx- p2_tx- p0_tx- p2_rx- p3_rx+ p1_rx- p 1 _ tx+ p 1 _ tx- p2_rx+ p0_rx+ p0_tx+ p0_rx- p2_tx+ p1_rx+ edo edi(sdio) eecs eesk(sdc) xo xi reset# p5_txd0 eesk(sdc) p5_txd3 p4_fx rst# p5_txd0 control p5_txd3 p1_rx- p2_rx- p2_tx- p3_rx- p0_tx- p3_rx+ p0_rx+ p2_rx+ p1_dupcol p0_dupcol p3_dupcol p4_dupcol p2_dupcol p0_ldspd p3_ldspd p2_ldspd p1_ldspd p4_ldspd p1_l/a_led p3_l/a_led p4_l/a_led p2_l/a_led p0_l/a_led p0_rx- p1_tx+ p0_tx+ p1_tx- p3_tx- p1_rx+ p3_tx+ p0_ldspd p1_ldspd p2_ldspd sd3 sd0 sd5 cs# sd4 sd14 sd2 sd7 cs# sd11 sd13 sd4 sd0 sd6 sd12 sd1 sd5 sd15 sd9 sd2 int iow# sd14 sd8 ior# sd3 sd10 cmd dm9ka_gpio0 dm9ka_gpio1 cpu_gpio1 cpu_gpio0 mii_mdio mii_mdc eesk(sdc) mdc mii_mdio mii_mdc mdi o edi(sdio) p4_rx+ tx+ rx+ p4_tx+ p4_tx- rx- tx- p4_rx- p2_tx+ p1_dupcol p0_dupcol p2_dupcol reset# r? 1k r? 1k r? 1k r? 1k r? 1k r? 10k x? 25mhz c? 20p r? 1m c? 20p r? 1k1% c? 0.1uf r? 1k c? 0.1uf c? 0.1uf d? led a c c? 0.1uf r? 1k c? 0.1uf + c? 220uf/6.3v ec-mr05-2 r? 10k r? 182 l? f.b/120/s0603 r? 10k jp? y cl ptc1411-31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 d? led a c d? led a c d? led a c r? 1k d? led a c d? led a c d? led a c d? led a c r? 182 d? led a c c? 0.1uf r? 182 d? led a c r? 182 d? led a c c? 0.1uf c? 0.1uf c? 0.1uf c? 0.1uf d? led a c d? led a c d? led a c d? led a c + c? 220uf/6.3v ec-mr05-2 c? 0.1uf r? 49.9 r? 49.9 r? 49.9 r? 0 c? 0.1uf r? 49.9 c? 0.1uf r? 0 c? 0.1uf u? 93lc46/93lc66/dip8 1 2 3 4 5 6 7 8 cs sk di do gnd nc nc vcc q? 2sb1386 b e c d? 1n4148 smd a c r? 1k r? 49.9 r? 49.9 c? 0.1uf r? 49.9 r? 49.9 c? 0.1uf c? 0.1uf c0603 c? 0.1uf c0603 c? 0.1uf c0603 c? 0.1uf c0603 r? 100k c? 0.1uf c0603 r? 6.8k1% r0603 r? 4.7k r0603 + c? 10uf/16v ec-mr05-2 u? dm8606af/qfp128 qfp128-1 104 105 106 108 107 110 114 111 96 95 121 120 119 118 94 93 92 91 90 89 88 87 86 85 83 82 81 80 79 78 77 76 68 67 66 64 63 62 60 58 57 56 54 53 52 51 49 48 47 45 44 7 9 10 11 12 14 15 16 17 19 20 22 23 24 25 27 28 29 30 32 33 34 36 37 38 40 113 112 116 123 125 127 128 1 2 4 5 41 43 42 75 73 72 71 97 103 70 6 98 3 8 13 18 21 35 31 26 65 69 74 84 99 100 101 102 39 46 50 61 59 55 126 124 122 117 115 109 p4_txd2 p4_txd1(p4ty pe1) p4_txd0(p4ty pe0) dgnd dphalfp4 dupcol3 p4_txen dupcol2(recbpen) lnkact2 lnkact3 xo xi reset# dgnd dvdd18 dgnd lnkfp4 dphalfp5 lnkfp5 spdtnp5 dvdd33 dgnd cfg0 cko25m dgnd dvdd18 eesk(xoven) eecs edi(dualcolor) p4_col p4_crs dgnd p5_rxer p5_txclk p5_txen(phyas0) dgnd (cfgen)p5_txd0 p4_fx p5_txd2 p5_col p5_crs p5_rxd3 p5_rxd1 p5_rxd0 p5_rxdv p4_spdtn dvdd33 ldspd3 ldspd2 dgnd md c p0_rx- avdd18 p1_tx+ p1_tx- agnd p1_rx+ p1_rx- avdd33 avdd18 p2_tx- agnd p2_rx- avdd33 avdd18 p3_tx+ agnd agnd p3_rx+ p3_rx- p4_rx- p4_rx+ agnd p4_tx- p4_tx+ avdd18 md i o dupcol0(recanen) dupcol1(phy as1) dvdd18 dgndpll vref rtx dvdd33bias avdd18 p0_tx+ agnd agnd test ldspd1 ldspd0 dvdd18 p4_rxdv p5_rxclk dvdd33 lnkact1 p4_txd3 dgnd p0_rx+ lnkact0 p0_tx- avdd33 agnd p2_tx+ p2_rx+ agnd avdd33 p3_tx- dvdd18 dgnd p4_rxd0 edo dgnd p4_rxd1 p4_rxd2 p4_rxd3 p4_rxer dvdd18 dgnd (p5_gpsi)p5_txd1 p5_txd3 p5_rxd2 dgndbias control dvdd18pll p4_rxclk p4_txcll dvdd33 c? 22pf c0603 y? 25mhz/49us xtal + c? 220uf/16v ec-mr05-2 dm9008a-8/16bit u? dm9008ae/lqfp48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 bgres avdd25 rx+ rx- agnd agnd tx+ tx- avdd25 sd7 sd6 sd5 sd4 sd3 gnd sd2 sd1 sd0 eedio eedck eedcs sd15 vdd sd14 sd13 sd12 sd11 sd10 sd9 vdd sd8 cmd gnd int ior# iow# cs# led2(iowait / wakeup for eeprom) led1(io16 for eeprom) pwrst# test vdd x2 x1 gnd sd agnd bggnd c? 0.1uf r? 49.9 + c? 330uf/16v ec-mr05-2 r? 49.9 c? 0.1uf r? 49.9 r? 49.9 c? 0.1uf r? 10k r0603 u? ap1084,to-263 3 1 2 vin g vout c? 0.1uf c0603 l? f.b/120/s0603 c? 0.1uf u? rt9172-25cm,to-263 1 2 3 vin g vout r? 1k r? 10k r? 0 r? 0 r? 69 + c? 220uf/6.3v ec-mr05-2 r? 69 r? 69 r? 69 + c? 220uf/6.3v ec-mr05-2 r? 10k c? 0.1uf r? 49.9 r? 49.9 c? 0.1uf r? 10k r? 0 r? nc r? 0 r? nc r? 1k r? 1k r? 1k c? 0.1uf r? 1k c? 0.1uf r? 1k c? 0.1uf r? 49.9 r? 49.9 c? 0.1uf c? 0.1uf c? 0.1uf c? 0.1uf + c? 1uf/6.3v ec-mr05-2 c? 22pf c0603 l? f.b/120/s0603 + c? 220uf/6.3v ec-mr05-2 c? 0.1uf u? 93lc46/dip8 1 2 3 4 5 6 7 8 cs sk di do gnd nc nc vcc reset# f or dm9000a sys_bus_sd1 sys_bus_sd6 sys_bus_sd14 sys_bus_sd5 sys_bus_sd12 sys_bus_ior# sys_bus_sd3 sys_bus_sd4 sys_bus_sd7 sys_bus_sd15 sys_bus_sd10 sys_bus_sd11 sys_bus_sd9 sys_bus_sd13 sys_bus_sd8 sys_bus_cs# sys_bus_sd2 sys_bus_sd0 sys_bus_int sys_bus_iow# sys_bus_cmd(sys_bus_sa2) cpu_gpio0 cpu_gpio1 reset# f or dm8606a preliminar y ( for reference onl y) enable auto-mdix enable flow control enable use sdc/sdio control enable prot 4 use fx reset for dm8606a and dm9008a system control bus select gpio of cpu to set dm8606a registor use smi interface set dm9000a software fix phy to fiber mode phyreg 0x00 ==> 0x2100 phyreg 0x10 ==> 0x4014 power 5v to 3.3v select gpio of dm9000a to set dm8606a registor pull high set dm8606a led mode and automdix
DM9008AEP ethernet controller with general processor interface preliminary 48 version: DM9008AEP-ds-p03 dec. 14, 2006 11.5 magnetics selection guide refer to table 1 for transformer requirements. transformers, meeting these requirements, are available from a variety of magnetic manufacturers. designers should test and qualify all magnetics before using them in an application. the transformers listed in table 1 are electrical equivalents, but may not be pin-to-pin equivalents. manufacturer part number pulse engineering pe-68515, h1078, h1012, h1102 delta lf8200, lf8221x ycl 20pmt04, 20pmt05, ph163112 , ycl 0303 ph163539 *(hp auto-mdix) magcom hs9001 , hs9016 halo tg22-3506nd, td22-3506g1, tg22-s010nd, tg22-s012nd tg110-s050n2 nano pulse inc. npi 6181-37, npi 6120-30, npi 6120-37 npi 6170-30 fil-mag pt41715 bel fuse s558-5999-01, s558-5999-w2 valor st6114, st6118 macronics hs2123, hs2213 bothhand ts6121c,16st8515,16st1086 table 1 11.6 crystal selection guide a crystal can be used to generate the 25mhz reference clock instead of an oscillator. the crystal must be a fundamental type, and series-resonant. connects to pins x1 and x2, and shunts each crystal lead to ground with a 22pf capacitor(see figure 11-3). figure 11-3 crystal circuit diagram 43 44 x1 x2 a gnd a gnd 22pf 25mhz 22pf
DM9008AEP ethernet controller with general processor interface preliminary 49 version: DM9008AEP-ds-p03 dec. 14, 2006 12. package information lqfp 48l (f.p. 2mm) outline dimensions unit: inches/mm z % % symbol dimensions in inches dimensions in mm min. nom. max. min. nom. max. a - - 0.063 - - 1.60 a 1 0.002 - 0.006 0.05 - 0.15 a 2 0.053 0.055 0.057 1.35 1.40 1.45 b 0.007 0.009 0.011 0.17 0.22 0.27 b1 0.007 0.008 0.009 0.17 0.20 0.23 c 0.004 - 0.008 0.09 - 0.20 c1 0.004 - 0.006 0.09 - 0.16 d 0.354bsc 9.00bsc d1 0.276bsc 7.00bsc e 0.354bsc 9.00bsc e1 0.276bsc 7.00bsc 0.020bsc 0.50bsc l 0.018 0.024 0.030 0.45 0.60 0.75 l1 0.039ref 1.00ref y 0.003max 0.08max notes: 1. to be determined at seating plane. 2. dimensions d1 and e 1do not include mold protrusion. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. dimensions b does not include dambar protrusion. total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. 4. exact shape of each corner is optional. 5. these dimensions apply to the flat section of the lead between 0.10mm and 0.25mm from the lead tip. 6. a1 is defined as the distance from the seating plane to the lowest point of the package body. 7. controlling dimension: millimeter. 8. reference documents: jedec ms-026, bbc. 0-12 0-12
DM9008AEP ethernet controller with general processor interface preliminary 50 version: DM9008AEP-ds-p03 dec. 14, 2006 13. ordering information part number pin count package DM9008AEP 48 lqfp(pb-free) disclaimer the information appearing in this publication is believed to be accurate. integrated circuits sold by davicom semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. davicom makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. further, davicom makes no warranty of merchantability or fitness for any purpose. davicom reserves the right to halt production or alter the specifications and prices at any time without notice. accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. products described herein are intended for use in normal commercial applications. applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by davicom for such applications. please note that application circuits illustrate d in this document are for reference purposes only. davicom?s terms and conditions printed on the order acknowledgment govern all sales by davicom. davicom will not be bound by any terms inconsistent with these unless davicom agrees otherwise in writing. acceptance of the buyer?s orders shall be based on these terms. company overview davicom semiconductor inc. develops and manufactures integrated circuits for integration into data communication products. our mission is to design and produce ic products that are the industry?s best value for data, audio, video, and internet/intranet applications. to achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. products we offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and ethernet networking standards. contact windows for additional information about davicom products, contact the sales department at: headquarters hsin-chu office: no.6 li-hsin rd. vi, science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-5798797 fax: 886-3-5646929 warning conditions beyond those listed for the absolute maximum may destroy or damage the products. in addition, conditions for sustai ned periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance a nd/or function.

▲Up To Search▲

Price & Availability of DM9008AEP

	To Download DM9008AEP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .